1) Field of the Invention
The present invention relates to the fabrication of semiconductor devices, and more specifically to a fabrication sequence used to from a self aligned contact (SAC) to a substrate for a metal oxide semiconductor field effect (MOSFET).
2) Description of the Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to reduce the cost of these same devices. These objectives have been successfully addressed by the ability of the semiconductor industry to practice micro-miniaturization, or to fabricate semiconductor devices with sub-micron features. Several fabrication disciplines, such as photolithography, as well as dry etching, have allowed micro-miniaturization to be realized. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist films, have allowed the attainment of sub-micron images in photoresist films, to be routine achieved. In addition the development of more advanced dry etching tools and processes, have allowed the sub-micron images, in masking photoresist films, to be successfully transferred to underlying materials used for the fabrication of semiconductor devices.
In addition to advances in semiconductor fabrication disciplines, several device structural innovations have also contributed to the quest for higher performing, lower cost, semiconductor devices. For example, the use of a self-aligned contact (SAC), procedure allows the amount of source and drain contact area to be reduced, thus allowing smaller devices to be constructed, resulting in faster, as well as lower cost devices, to be realized. The SAC procedure, using a sub-micron ground rule, opens a sub-micron region in an insulator layer, exposing an underlying source and drain region. However only a portion of the sub-micron SAC opening is used to expose the underlying source and drain region, with the remainder of the sub-micron SAC opening overlapping an adjacent polysilicon gate structure. Therefore the source and drain contact region is smaller then the SAC opening. If the contact opening to the source and drain was to made entirely overlaying the source and drain region, the source and drain region would have to be designed larger, to accommodate the fully landed contact hole opening, thus resulting in a undesirable, larger semiconductor device. In addition to the cost and performance benefits of devices fabricated using the SAC procedure, a dielectric sidewall spacer can also be used, allowing the SAC opening to be created, exposing the insulator sidewall of a polysilicon gate structure.
As shown in FIG. 4, a problem the inventor has found is that keyholes 124 are formed in ILD layers 36 when the spacing 62 between conventional spacers 110 is small. FIG. 4 shows gates 24, which can comprise several layers, with conventional spacers 110 formed on the sidewalls. Conventional spacers 110 have a width between 800 and 2000 .ANG.. A substrate 10 has STI regions 20 formed therein. A self aligned contact (SAC) plug 54 is formed to contact the substrate. The poly lines 24 are spaced closer in areas away from the SAC plug 54.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,648,291 (Sung) shows a spacer formed on the sidewalls of contact.
U.S. Pat. No. 5,565,372 (Kim) shows a contact having a spacer.
U.S. Pat. No. 5,766,992 (Chou et al.) shows a contact process with extra SiN spacers over the gate.
U.S. Pat. No. 5,731,236 (Chou et al.) and U.S. Pat. No. 5,807,779 (Liaw) show other self aligned contact (SAC) processes.